multisim bcd to 7 segment display decoder pin out

The Timer 555 produces high and low signals at frequent intervals, resulting in oscillating signal whose frequency is based on the values of two resistors and the charging capacitor. The circuit operation begins once the normally open switch is changed to closed position. The outputs of each Decoder ICs 4511 are connected to the 7 Segment display. This is done by connecting the outputs of each counter IC to the inputs of BCD to 7 Segment Decoder. The third part involves designing the display circuits.

We achieve again by designing a simple logic circuit consisting of another AND gate IC, whose inputs are connected to pins Q3 and Q2 of the second counter. This can be done by ensuring the second counter resets once the count reaches a value of 5. Here our requirement is to display the clock pulses till count of 60. Here we are using an AND gate IC 7408 whose inputs are connected to pins Q1 and Q4 of the first counter and output is connected to the U/D pin of second counter. In other words for a count of 9, Q1 and Q4 are at high logic signals. Recalling from the counter truth table, for a clock pulse count of 9, the corresponding binary count or status of counter output signal is 1001. Since our concern is to start the second counter once the first counter reaches the count value of 9, we accomplish this by designing a simple combinational logic circuit. The carry out pin of one of the IC is connected to the carry in pin of another IC. This is achieved by connecting the clock pins of the counter ICs to the output of 555 Timer, resulting in parallel clock input signals. Second part of designing involves connecting the two counters IC – 4510 in synchronous cascading arrangement. Here we get a 100uF electrolyte capacitor. With the frequency of output signal given by f = 1.44/ (Ra+Rb) C, we can calculate the values of C, assuming values of Ra and Rb to be around 10K. Here the required time period is 1 second.

Digital Stopwatch Circuit Diagram: Circuit Diagram of Digital Stop Watch Digital Stopwatch Circuit Design:įirst part of design involves designing the astable multivibrator arrangement of 555 Timer. The counter ICs connected in cascading format and each counter output is connected to BCD to 7 segment decoder used to drive the 7 segment displays. While the first counter counts from 0 to 9, the second counter starts its counting operation every time the count value of first counter reaches 9. This is done by using a 555 Timer IC connected in astable mode to produce the clock pulses of 1 second interval each.

The idea is to display clock pulses count from 0 to 59, representing a 60 second time interval. This circuit is based on the principle of 2 stage counter operation, based on synchronous cascading.

Multisim bcd to 7 segment display decoder pin out